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[ak4345] ms0635-e-01 2010/09 - 1 - general description the ak4345 is a 24bit low voltage and low power stereo dac with an integrated di gital audio interface transmitter. the ak4345 uses an advanced multi-bit ? architecture, which achieves 100db dynamic range at 3.3v operation. the ak4345 integrates both switched-capacit or and continuous time filters, enabling performance for systems that have excessive cl ock jitter. the output voltage level can be set as high as 1vrms. the ak4345 is offered in a space saving 16pin tssop package. features ? sampling rate: 8khz 96khz ? 24-bit 8 times fir digital filter ? scf with high tolerance to clock jitter ? single-ended output buffer ? digital de-emphasis for 32khz, 44.1khz, 48khz sampling ? i/f format: 24-bit msb justified, 16/24-bit lsb justified, i 2 s compatible ? master clock: 512/768/1024/1536fs for half speed (8khz 24khz) 256/384/512/768fs for normal speed (8khz 48khz) 128/192/256/384fs for double speed (48khz 96khz) ? p interface: 4-wire/3-wire ? dit bypass mode ? cmos input level ? thd+n: -90db ? dr, s/n: 100db ? dac output voltage level: 1vrms (@vdd=3.3v) ? dit - aes3, iec60958, s/pdif, eiaj cp1201 compatible - 1-channel transmission output - 42-bit channel status buffer ? power supply: 2.7 to 3.6v ? ta = ? 20 85 c ? 16pin tssop 100db 96khz 24-bit stereo 3.3v dac with dit ak4345
[ak4345] ms0635-e-01 2010/09 - 2 - lrc k bic k test audio data interface mclk pdn ? modulator lout 8x interpolator scf lpf rout v dd v ss v com de-emphasis control clock divider ? modulator 8x interpolator scf lpf dit t x csn ccl k cdti cdto p interface sdti1 figure 1. ak4345 block diagram (mode= ?0?) lrc k bic k test audio data interface mclk pdn ? modulator lout 8x interpolator scf lpf rout v dd v ss v com de-emphasis control clock divider ? modulator 8x interpolator scf lpf dit t x csn ccl k cdti p interface sdti1 sdti2 figure 2. ak4345 block diagram (mode= ?1?)
[ak4345] ms0635-e-01 2010/09 - 3 - ordering guide ak4345et ? 20 +85 c 16pin tssop (0.65mm pitch) akd4345 evaluation board for ak4345 pin layout 1 mclk lrc k bic k csn ccl k cdti ak4345 top view 2 3 4 5 6 7 8 test1 tx vdd cdto/ sdti2 vss vcom lout rout 16 15 14 13 12 11 10 9 pdn sdti1
[ak4345] ms0635-e-01 2010/09 - 4 - pin/function no. pin name i/o function 1 mclk i master clock input pin 2 bick i audio serial data clock pin 3 sdti1 i audio serial data input pin1 4 lrck i input channel clock pin 5 pdn i full power down mode pin ?l? : power down, ?h? : power up 6 csn i chip select pin 7 cclk i control data clock pin 8 cdti i control data input pin 9 test1 i test pin this pin must be open. 10 rout o rch analog output pin, the output is ?hi-z? when pdn pin = ?l?. 11 lout o lch analog output pin, the output is ?hi-z? when pdn pin = ?l?. 12 vcom o common voltage output pin, 0.5 vdd normally connected to vss with a 4.7 f (min. 1 f, max. 10 f) electrolytic capacitor. the output is ?l? when pdn pin = ?l?. 13 vss - ground pin 14 vdd - power supply pin, 2.7 3.6v cdto o control data output pin, the output is ?hi-z? when pdn pin = ?l?. 15 sdti2 i audio serial data input pin2 16 tx o transmit channel output pin, the output is ?l? when pdn pin = ?l?. note: all digital input pins should not be left floating.
[ak4345] ms0635-e-01 2010/09 - 5 - absolute maximum ratings (vss=0v; note 1 ) parameter symbol min max units power supply vdd ? 0.3 4.6 v input current, any pin except supplies iin - 10 ma digital input voltage ( note 2 )vind ? 0.3 vdd+0.3 v ambient temperature (powered applied) ta ? 20 85 c storage temperature tstg ? 65 150 c note 1. all voltages with respect to ground. note 2. mclk, bick, sdti1, lrck , pdn, csn, cclk, cdti, sdti2 warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss=0v; note 1 ) parameter symbol min typ max units power supply vdd 2.7 3.3 3.6 v note 1. all voltages with respect to ground. warning: akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4345] ms0635-e-01 2010/09 - 6 - analog characteristics (ta=25 c; vdd=3.3v; vss=0v; fs=44.1khz, 96khz; bick=64fs; signal frequency=1khz; 24bit data; measurement frequency=20hz 20khz at fs=44.1khz, 20hz 40khz at fs=96khz; unless otherwise specified) parameter min typ max units dynamic characteristics (gain bit= ?1?) : resolution 24 bits thd+n fs=44.1khz bw=20khz 0dbfs ? 60dbfs -90 ? 37 -80 - db db fs=96khz bw=40khz 0dbfs ? 60dbfs -88 ? 34 - - db db dr ( ? 60dbfs with a-weighted) 92 100 db s/n (a-weighted) 92 100 db interchannel isolation 80 100 db dc accuracy: interchannel gain mismatch 0.2 0.5 db gain drift 100 - ppm/ c output voltage: gain bit= ?1? ( note 3) 2.60 2.8 3.0 vpp output voltage: gain bit=?0? ( note 4 ) 2.05 2.2 2.35 vpp load resistance ( note 5 ) 10 k load capacitance 25 pf power supplies power supply current normal operation (pdn pin = ?h?, fs=44.1khz) ( note 6) normal operation (pdn pin = ?h?, fs=96khz) ( note 6) full power-down mode (pdn pin = ?l?) ( note 7) 7.0 8.5 10 12.8 50 ma ma a note 3. full-scale voltage (0db). output voltage scales with the voltage of vdd, vout = 0.85 vdd (typ). note 4. full-scale voltage (0db). output voltage scales with the voltage of vdd, vout = 0.67 vdd (typ). note 5. for ac-load. note 6. rstn bit= ?1?, pw bit= ?1?, tx pin: open. when tx pin = 20pf, power supply current (idd@3.3v) is 9.0ma(typ)@fs= 96khz. note 7. all digital input pins are fixed to vdd or vss.
[ak4345] ms0635-e-01 2010/09 - 7 - filter characteristics (ta=25 c; vdd=2.7 3.6v; fs=44.1khz; dem1 bit= ?0?, dem0 bit= ?1?) parameter symbol min typ max units dac digital filter: passband ( note 8 ) 0.05db ? 6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 8 ) sb 24.1 khz passband ripple pr 0.01 db stopband attenuation sa 54 db group delay ( note 9 ) gd - 24.0 - 1/fs digital filter + scf + ctf: frequency response 0 20khz 40khz ( note 10 ) fr - - 0.1 0.2 - - db db note 8. the passband and stopband frequencies scale with fs (system sampling rate). note 9. the calculating delay time which occurred by digital filtering. this time is from setting the 16/24bit data of both channels to input register to the output of analog signal. note 10. at fs=96khz. dc characteristics (ta=25 c; vdd=2.7 3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vdd - - - - 30%vdd v v high-level output voltage (iout=-80 a) low-level output voltage (iout=80a) voh1 vol1 vdd-0.4 - - - - 0.4 v v input leakage current iin - - 10 a tx characteristics (ta=25 c; vdd=2.7 3.6v) parameter symbol min typ max units high-level output voltage ( iout=-400 a) low-level output voltage ( iout=400 a) voh2 vol2 vdd-0.4 - - - - 0.4 v v load capacitance cl - - 50 pf
[ak4345] ms0635-e-01 2010/09 - 8 - switching characteristics (ta=25 c; vdd=2.7 3.6v; c l = 20pf) parameter symbol min typ max units master clock frequency half speed mode (512/768/1024/1536fs) normal speed mode (256/384/512/768fs) double speed mode (128/192/256/384fs) duty cycle fclk fclk fclk dclk 4.096 2.048 6.144 40 36.864 36.864 36.864 60 mhz mhz mhz % lrck frequency half speed mode (dfs1-0 = ?10?) normal speed mode (dfs1-0 = ?00?) double speed mode (dfs1-0 = ?01?) duty cycle fsh fsn fsd dclk 8 8 48 45 24 48 96 55 khz khz khz % audio interface timing bick period half speed mode normal speed mode double speed mode bick pulse width low pulse width high bick ? ? to lrck edge ( note 11 ) lrck edge to bick ? ? ( note 11 ) sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fs 1/128fs 1/64fs 70 70 40 40 40 40 ns ns ns ns ns ns ns ns ns control interface timing cclk period cclk pulse width low pulse width high cdti setup time cdti hold time csn ?h? time csn ? ? to cclk ? ? cclk ? ? to csn ? ? cdto delay csn ? ? to cdto hi-z tcck tcckl tcckh tcds tcdh tcsw tcss tcsh tdcd tccz 200 80 80 40 40 150 150 50 45 70 ns ns ns ns ns ns ns ns ns ns power-down & reset timing pdn pulse width ( note 12 ) tpd 4 ms/ f note 11. bick rising edge must not occur at the same time as lrck edge. note 12. the ak4345 can be reset by bringing pdn pin = ?l?. the pdn pulse width is proportional to the value of the capacitor (c) connected to vcom pin. tpd = 4000 c. when c = 4.7 f, tpd is 19ms(min). the value of the capacitor (c) connected with vcom pin should be 1 f c 10 f.
[ak4345] ms0635-e-01 2010/09 - 9 - timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 3. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 4. serial interface timing
[ak4345] ms0635-e-01 2010/09 - 10 - tcckl csn cclk tcds cdti tcdh tcss c0 a4 tcckh cdto hi-z r/w c1 vih vil vih vil vih vil tcck figure 5. write/read command input timing in 3-wire/4-wire serial mode tcsw csn cclk cdti d2 d0 tcsh cdto hi-z d1 d3 vih vil vih vil vih vil figure 6. write data input timing in 3-wire/4-wire serial mode csn cclk tdcd cdto d7 d6 cdti a1 a0 d5 hi-z 50%vdd vih vil vih vil vih vil figure 7. read data output timing 1 in 4-wire serial mode
[ak4345] ms0635-e-01 2010/09 - 11 - csn cclk tccz cdto d2 d1 cdti d0 d3 tcsw tcsh 50%vdd vih vil vih vil vih vil hi-z figure 8. read data output timing 2 in 4-wire serial mode tpd vil pdn figure 9. power-down & reset timing
[ak4345] ms0635-e-01 2010/09 - 12 - operation overview system clock the external clocks, which ar e required to operate the ak4345, are mclk , bick and lrck. the master clock (mclk) should be synchronized with lrck but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. the mclk frequency is detected from the relation between mclk and lrck automatically. the half speed, the norm al speed and the double speed mode ar e selected with th e dfs1-0 bits ( table 1 ). the sampling speed mode is set depending on the mclk frequency automatically for auto mode (dfs1 bit = dfs0 bit = ?1?) ( table 2 ). the ak4345 is automatically pl aced in the reset mode when mclk stops in the normal operation m ode (pdn pin = ?h?), and the analog output becomes the vcom voltage. after mclk is input again, the ak4345 is powered up. after exiting reset by pdn pin at power-up etc., the ak4345 is in the reset mode until mclk and lrck are input. mode dfs1 dfs0 fs mclk frequency normal speed 0 0 8 48khz 256/384/512/768fs double speed 0 1 48 96khz 128/192/256/384fs half speed 1 0 8 24khz 512/768/1024/1536fs auto 1 1 8 96khz table 2 table 1. system clock example mclk frequency sampling speed mode fs 512/768fs normal speed 8 48khz 128/192/256/384fs double speed 48 96khz 1024/1536fs half speed 8 24khz table 2. auto mode audio interface format the data is shifted in via the sdti pin using bick and lrck inputs. the dif1-0 bits as shown in table 3 can select four serial data modes. in all modes the serial data is msb-first, 2?s compliment format and is latched on the rising edge of bick. mode 3 can be used for 16bit i 2 s compatible format by zeroing the unused lsbs at bick 48fs or bick = 32fs. mode dif1 dif0 sdti format bick figure 0 0 0 16bit, lsb justified 32fs figure 10 1 0 1 24bit, lsb justified 48fs figure 11 2 1 0 24bit, msb justified 48fs figure 12 3 1 1 16/24bit, i 2 s compatible 48fs or 32fs figure 13 table 3. audio interface format
[ak4345] ms0635-e-01 2010/09 - 13 - lrck bick(32fs) 0 110 2 3 9 1112131415 0 12 3 1 0 10 9 1112131415 sdti(i) don't care 1 0 15 14 13 210 15 14 13 12 12 don't care sdti-15:msb, 0:lsb sdti(i) 15 14 13 76543 210 15 14 13 15 76543 210 bick(64fs) 0 118 2 3 19 20 31 0 1 2 3 1 0 18 19 20 31 17 17 lch data rch data figure 10. mode 0 timing lrck bick(64fs) 0 1 224310 12 1 0 31 24 89 89 sdti(i) don't care 0 8 10 23:msb, 0:lsb lch data rch data 23 8 don't care 23 1 figure 11. mode 1 timing lrck bick(64fs) 0 1 2202124310 12 1 0 22 20 21 31 24 22 23 23 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 23 1 2 3 4 figure 12. mode 2 timing lrck bick(64fs) 0 1 225 21 24 0 12 1 0 22 25 21 24 22 23 23 3 sdti(i) don't care 0 0 23:msb, 0:lsb lch data rch data don't care 4321 23 22 23 22 1 2 3 4 figure 13. mode 3 timing
[ak4345] ms0635-e-01 2010/09 - 14 - data transmission format data transmitted on the tx outputs is formatted in blocks as shown in figure 14 . each block consists of 192 frames. a frame of data contains two sub-frames. a sub-frame consists of 32 bits of information. e ach received data bit is coded using a bi-phase mark encoding as a two binary state symbol. the preambles violate bi-phase encoding so they may be differentiated from data. in bi-phase encoding, the first state of an input symbol is always the inverse of the last state of the previous data symbol. for a logic 0, the second state of th e symbol is the same as the fi rst state. for a logic 1, the second state is the opposite of the first. figure 15 illustrates a sample stream of 8 data bits encoded in 16 symbol states. frame 191 frame 0 frame 1 sub-frame sub-frame m channel 1 w channel 2 b channel 1 w channel 2 m channel 1 w channel 2 figure 14. block format 0 1 1 0 0 0 1 0 figure 15. a biphase-encoded bit stream the sub-frame is defined in figure 16 below. bits 0-3 of the sub-frame represent a preamble for synchronization. there are three preambles. the block preamble, b, is contained in the first sub-frame of frame 0. the channel 1 preamble, m, is contained in the first sub-frame of all other frames. the channel 2 preamble, w, is contained in all of the second sub-frames. table 4 below defines the symbol encoding for each of the preambles. bits 4-27 of the sub-frame contain the 24 bit audio sample in 2?s complement format with bit 27 as the most signifi cant bit. for 16 bit mode, bits 4-11 are all 0. bit 28 is the validity flag. this is ?h? if the audio sample is unreliable. bit 29 is a user data bit. frame 0 contains the first bit of a 19 2 bit user data word. frame 191 contains the last bit of the us er data word. bit 30 is a channel status bit. again frame 0 contains the first bit of the 192 bit word with the last bit in frame 191. bit 31 is an even parity bit for bits 4-31 of the sub-frame. sync p c u v l m s audio sample s b b 0 3 4 27 28 29 30 31 figure 16. sub-frame format the block of data contains consecutive fr ames transmitted at a state-bit rate of 64 times the sample frequency, fs. for stereophonic audio, the left or a channel data is in channel 1 while the right or b data is in channel 2. for monophonic audio, channel 1 contains the audio data. preamble preceding state = 0 preceding state = 1 b 11101000 00010111 m 11100010 00011101 w 11100100 00011011 table 4. sub-frame preamble encoding channel status bit in the consumer mode (bit0 = ?0?), bits20-23(audio channel) must be controlled by the cs20 bit. when the cs20 bit is ?1?, the ak4345 corresponds to ?stereo mode?, bits20-23 are se t to ?1000?(left channel) in sub-frame 1, and is set to ?0100?(right channel) in sub-frame 2. when the cs20 bit is ?0?, bits20-23 is set to ?0000? in both sub-frame 1 and sub-frame 2.
[ak4345] ms0635-e-01 2010/09 - 15 - de-emphasis filter a digital de-emphasis filter is available for 32, 44.1 or 48 khz sampling rates (tc = 50/15s) and is controlled by dem0 and dem1. in double speed and quad speed mode, the digital de-emphasis filter is always off. dem1 dem0 mode 0 0 44.1khz 0 1 off (default) 1 0 48khz 1 1 32khz table 5. de-emphasis filter control (normal speed mode) power-down the ak4345 is placed in the powe r-down mode by bringing pdn pin = ?l?. and the digital filter is reset at the same time. this reset should always be done after power up. normal operation internal state pdn power-down normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (2) (4) external mute (6) (4) (2) mute on (3) (5) don?t care (1) notes: (1) pdn pin should be ?l? for 19ms or mo re when an electro lytic capacitor 4.7 f is attached between vcom pin and vss. (2) the analog output corresponding to digital input has the group delay (gd). (3) when pdn pin = ?l?, the analog output is hi-z. (4) click noise occurs in 3 4lrck at both edges ( ) of pdn signal. this noise is output even if ?0? data is input. (5) the external clocks (mclk, bick and lrck) can be stopped in the power down mode (pdn pin = ?l?). (6) please mute the analog output externally if the click noise (4) influences system application. the timing example is shown in this figure. figure 17. power-down/up sequence example
[ak4345] ms0635-e-01 2010/09 - 16 - reset function (1) reset by rstn bit when rstn bit =0, dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage figure 18 shows the example of reset by rstn bit. internal state rstn bit digital block p d normal operation gd gd ?0? data d/a out (analog) d/a in (digital) clock in mclk,lrck,bick (1) (3) (3) (1) (2) normal operation internal rstn bit 2~3/fs (6) 3~4/fs (6) don?t care (4) notes: (1) the analog output corresponding to digital input has the group delay (gd). (2) analog outputs go to vcom voltage (vdd/2). (3) click noise occurs at the edges(? ?) of the internal timing of rstn bit. th is noise is output even if ?0? data is input. (4) the external clocks (mclk, bick and lrck) can be stopped in the reset mode (rstn bit = ?0?). (5) there is a delay, 3~4/fs from rstn bit ?0? to the inte rnal rstn bit ?0?, and 2~3/fs from rstn bit ?1? to the internal rstn bit ?1?. figure 18. reset sequence example1
[ak4345] ms0635-e-01 2010/09 - 17 - (2) reset by mclk stop (pdn pin = ?h?) when mclk stops, dac is powered down but the internal register values are not initialized. the analog outputs go to vcom voltage. normal operation internal state reset normal operation gd gd d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (2) (3) external mute (6) vcom (2) mclk stop pdn pin power-down power-down (4) (4) (4) hi-z (6) (6) (5) (1) notes: (1) pdn pin should be ?l? for 19ms or mo re when an electro lytic capacitor 4.7 f is attached between vcom pin and vss. (2) the analog output corresponding to digital input has the group delay (gd). (3) the digital data can be stopped. the click noise after mclk is input again by inputting the ?0? data to this section can be reduced. (4) click noise occurs in 3 4lrck at both edges ( ) of pdn signal, mclk inputs an d mclk stops. this noise is output even if ?0? data is input. (5) the external clocks (bick and lrck) can be stopped in the power down mode (mclk stop). (6) please mute the analog output externally if the click noise (4) influences system app lication. the timing example is shown in this figure. figure 19. reset sequence example 2
[ak4345] ms0635-e-01 2010/09 - 18 - p control interface the ak4345 can select 4-wire p i/f mode (mode bit = ?0?) or 3-wire p i/f mode (mode bit = ?1?). 1.4-wire p i/f mode (mode bit = ?0?, default) the internal registers may be either written or read by the 4-wire p interface pins: csn, ccl k, cdti and cdto. the data on this interface consists of chip ad dress (2bits, c1/0; fixed to ?01?), read/wr ite (1bit), register address (msb first, 5bits) and control data (msb first, 8bits). address and data are clocked in on the rising edge of cclk and data is clocked out on the falling edge. for write operatio ns, data is latched after the 16th rising edge of cclk, after a high-to-low transition of csn. csn should be set to ?h? once after 16 cclks. for read operations, the cdto output goes high impedance after a low-to-high transition of csn. the ma ximum speed of cclk is 5mhz. pdn pin = ?l? resets the registers to their default values. cdti cclk csn c1 0 1 2 34567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/ w c0 a 0 d0 d1 d2 d3 cdto hi-z write cdti c1 d4 d5 d6 d7 a1 a2 a3 a4 r/ w c0 a 0 d0 d1 d2 d3 cdto hi-z read d4 d5 d6 d7 d0 d1 d2 d3 hi-z c1-c0: chip address: (fixed to ?01?) r/w: read/write (0:read, 1:write) a4-a0: register address d7-d0: control data figure 20. 4-wire seri al control i/f timing *when the ak4345 is in the power down mode (pdn pin = ?l?) or the mclk is not provided, writing into the control register is inhibited.
[ak4345] ms0635-e-01 2010/09 - 19 - 2.3-wire p i/f mode (mode bit = ?1?) internal registers may be written by 3-wire p interface pins , csn, cclk and cdti. the data on this interface consists of chip address (2bits, c1/0; fixed to ? 01?), read/write (1bit; fixed to ?1?, write only), register address (msb first, 5bits) and control data (msb first, 8bits). ak4345 latches the data on the rising edge of cclk, so data should clocked in on the falling edge. the writing of data becomes valid by 16th cclk after a high to low transition of csn. csn should be set to ?h? once after 16 cclks for each address. the clock speed of cclk is 5mhz (max). pdn pin = ?l? resets the registers to their default values. the in ternal timing circuit is reset by rstn bit, but the registers are not initialized. cdti cclk csn c1 0 1234567 8 9 10 11 12 13 14 15 d4 d5 d6 d7 a1 a2 a3 a4 r/w c0 a0 d0 d1 d2 d3 c1-c0: chip address (fixed to ?01?) r/w: read/write (fixed to ?1?, write only) a4-a0: register address d7-d0: control data figure 21. control i/f timing *the ak4345 does not support the read command and chip address. c1/0 and r/w are fixed to ?011? *when the ak4345 is in the power down mode (pdn pin = ?l?) or the mclk is not provided, writing into the control register is inhibited. dac and dit input select the ak4345 can select 4-wire p i/f mode (mode bit = ?0?) or 3-wire p i/f mode (mode bit = ?1?). in 3-wire p i/f mode, the ak4345 can select the input data of dac and dit from sdti1 or sdti2 data. mode sel1 sel0 p i/f dac input dit input 0 x x 4-wire sdti1 sdti1 1 0 0 3-wire sdti1 sdti1 1 0 1 3-wire sdti2 sdti2 1 1 0 3-wire sdti2 bypass 1 1 1 reserved (x: don?t care) table 6. dac and dit input
[ak4345] ms0635-e-01 2010/09 - 20 - register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 1 0 0 0 dif1 dif0 pw rstn 01h control 2 0 1 0 dfs1 dfs0 dem1 dem0 gain 02h control 3 0 0 0 invl invr mode sel1 sel0 03h tx 0 0 0 0 0 0 v txe 04h channel status byte0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 05h channel status byte1 cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 06h channel status byte2 cs23 cs22 cs21 cs20 cs19 cs18 cs17 cs16 07h channel status byte3 cs39 cs38 cs37 cs36 cs35 cs34 cs33 cs32 08h channel status byte4 cs39 cs38 cs37 cs36 cs35 cs34 cs33 cs32 09h channel status byte5 0 0 0 0 0 0 cs41 cs40 notes: for addresses from 0ah to 1fh, data must not be written. when pdn pin goes ?l?, the registers are initialized to their default values. when rstn bit goes ?0?, the only internal timing is re set and the registers are not initialized to their default values. all data can be written to the regist er even if pw or rstn bit is ?0?. the bits shown as ?0? should be written ?0? and the bits shown as ?1? should be written ?1?. register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h control 1 1 0 0 0 dif1 dif0 pw rstn r/w r/w default 1 0 0 0 1 1 1 1 rstn: internal timing reset control 0: reset. all registers are not initialized. 1: normal operation when mclk frequency or dfs changes the click noise occurs. it can be reduced by rstn bit. pw: power down control 0: power down. all registers are not initialized. 1: normal operation dif1-0: audio data interface formats ( table 3) initial: ?11?, mode 3
[ak4345] ms0635-e-01 2010/09 - 21 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h control 2 0 1 0 dfs1 dfs0 dem1 dem0 gain r/w r/w default 0 1 0 1 1 0 1 1 dem1-0: de-emphasis response ( table 5) initial: ?01?, off dfs1-0: sampling speed control 00: normal speed 01: double speed 10: half speed 11: auto (default) when changing between normal/double speed mode and half speed mode, some click noise occurs. gain: output voltage scale 0: vout = 0.67 vdd (typ) at full-scale voltage (0db) . 1: vout = 0.85 vdd (typ) at full-scale voltage (0db) . register name d7 d6 d5 d4 d3 d2 d1 d0 02h control 3 0 0 0 invl invr mode sel1 sel0 r/w r/w default 0 0 0 0 0 0 0 0 invr: inverting lch output polarity 0: normal output 1: inverted output invl: inverting rch output polarity 0: normal output 1: inverted output mode: mode control 0: 4 wire mode 1: 3 wire mode sel1-0: dac and dit input 00: sdti1 input 01: sdti2 input 10: sdti2 input (dit bypass) 11: reserved sel1-0 bits are disabled in 4-wire p i/f mode (mode bit = ?0?). sdti1 data is input to both dac and dit.
[ak4345] ms0635-e-01 2010/09 - 22 - register name d7 d6 d5 d4 d3 d2 d1 d0 03h tx 1 0 0 0 0 0 v txe r/w r/w default 1 0 0 0 0 0 0 1 v: validity flag 0: valid 1: invalid txe: tx output 0: ?l? 1: normal operation register name d7 d6 d5 d4 d3 d2 d1 d0 04h channel status byte0 cs7 cs6 cs5 cs4 cs3 cs2 cs1 cs0 default 0 0 0 0 0 1 0 0 05h channel status byte1 cs15 cs14 cs13 cs12 cs11 cs10 cs9 cs8 default 0 0 0 0 0 0 0 0 06h channel status byte2 cs23 cs22 cs21 cs20 cs19 cs18 cs17 cs16 default 0 0 0 0 0 0 0 0 07h channel status byte3 cs31 cs30 cs29 cs28 cs27 cs26 cs25 cs24 default 0 0 0 0 0 0 0 0 08h channel status byte4 cs39 cs38 cs37 cs36 cs35 cs34 cs33 cs32 default 0 0 0 0 0 0 0 0 09h channel status byte5 0 0 0 0 0 0 cs41 cs40 default 0 0 0 0 0 0 0 0 cs7-0: transmitter channel status byte 0 default: ?00000100? cs39-8: transmitter channel status byte 4-1 default: ?00000000? cs41-cs40: transmitter channel status byte 5 default: ?00000000?, d7-d2 bits should be written ?0?.
[ak4345] ms0635-e-01 2010/09 - 23 - system design figure 22 and figure 23 shows the system connection diagram. th e evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. mclk 1 bick 2 sdti 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 tx 16 cdto 15 vdd 14 vss 13 vcom 12 lout 11 rout 10 test1 9 master clock ak4345 fs 24bit audio data reset & power down 64fs 4.7u 0.1u + rch out lch out analog ground digital ground a nalog suppl y 2.7 to 3.6v + 10u optic transmitting module micro controller 300 figure 22. typical connection diagram (mode bit = ?0?, 4 wire mode ) mclk 1 bick 2 sdti 3 lrck 4 pdn 5 csn 6 cclk 7 cdti 8 tx 16 sdti2 15 vdd 14 vss 13 vcom 12 lout 11 rout 10 test1 9 master clock ak4345 fs 24bit audio data1 reset & power down 64fs 4.7u 0.1u + rch out lch out analog ground digital ground a nalog suppl y 2.7 to 3.6v + 10u optic transmitting module micro controller 300 24bit audio data2 figure 23. typical connection diagram (mode bit = ?1?, 3 wire mode )
[ak4345] ms0635-e-01 2010/09 - 24 - 1. grounding and power supply decoupling the ak4345 requires careful attention for power supply and grounding arrangements. vdd is usually supplied from the analog supply in the system. system anal og ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4345 as possible, with the small value ceramic capacitor being the closest. 2. voltage reference the differential voltage between vdd and vss sets the analog output range. vcom is used as a common voltage of the analog signal. vcom pin is a signal ground of this chip. an electrolytic capacitor about 4.7 f should be attached between vcom pin and vss. no load current may be drawn from vcom pin. especially, the ceramic capacitor should be connected to this pin as near as possible. 3. analog outputs the analog outputs are single-ended and ce ntered around the vcom voltage (0.5 vdd). the output signal range is typically 2.8vpp (typ@vdd=3.3v). the internal switched-capac itor filter and continuous-time filter attenuate the noise generated by the delta-sigma modulator beyond the audio passband. the output voltage is a positive full scale for 7fffffh (@24bit) and a negative full scale for 800000h (@24bit). the ideal output is vcom voltage (0.5 vdd) for 000000h (@24bit). dc offsets on analog outputs are eliminated by ac coupling since analog outputs have dc offsets of vcom + a few mv. figure 24 shows an example of the external lpf with 2.8vpp (1vrms) output. lout / rout 10u 220 1nf ak4345 22k 2.8vpp (1vrms) analog out fc=723.4khz, g=-0.013db at 40khz figure 24. external 1 st order lpf circuit example
[ak4345] ms0635-e-01 2010/09 - 25 - package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.1 (max) a 1 8 9 16 16pin tssop (unit: mm) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder (pb free) plate
[ak4345] ms0635-e-01 2010/09 - 26 - marking akm 4345et xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4345et 4) asahi kasei logo revision history date (yy/mm/dd) revision reason page contents 07/06/20 00 first edition 10/09/28 01 specification change 25 package the package dimensions were changed.
[ak4345] ms0635-e-01 2010/09 - 27 - important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application examples of the semiconductor products. you are fully responsible for the incorporatio n of these external circuits, application circuits, software and other related information in the design of your equipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of such information contained herein. z any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor auth orized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products, who distri butes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

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